1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and, particularly to a configuration of a decoder and an associated circuit that select and drive a word line. Specifically, the present invention relates to a configuration of a highly-integrated decoder portion that operates stably even when a high voltage is applied.
2. Description of the Background Art
A flash memory is excellent in portability and impact-resistance, and has characteristics of being electrically and collectively erasable. Therefore, in recent years, demand for the flash memory has been rapidly increased as a file storage of small portable information equipment such as a portable personal computer and a digital still camera.
One example of an array configuration of such a flash memory is shown in Reference 1 (Japanese Patent Laying-Open No. 2003-141887). In the configuration shown in Reference 1, a plurality of blocks, each including sub-arrays each having memory cells arranged in rows and columns, are provided. In the sub-arrays of each block, word lines are provided for the memory cells aligned in a row direction. Sources and drains of the memory cells aligned in a column direction are connected in common by using diffusion layers, respectively.
Drain diffusion layer interconnection is coupled to a global bit (data) line through a first block selection transistor that responds to a first block selection signal. Source diffusion layer interconnection is connected to a common source line through a second block selection transistor that passes current in response to a second block selection signal. These global bit line and the common source line are provided in common for the plurality of blocks, and writing/reading of data with respect to memory cells is executed in a selected block. Through the use of the diffusion layers as the drain line and the source line, a contact between the memory cells and a global bit line or between the common source line and metal interconnection can be shared by a plurality of memory cells aligned in the column direction, which can reduce a layout area of the memory cells (only one contact is necessary for one memory cell column).
Moreover, in the configuration shown in Reference 1, a word line decoding circuit for driving a word line into a selected state is configured into a hierarchical structure of a block decoder, a gate decoder and a sub-decoder for high speed operation. The block decoder selects a block and also generates a voltage transmitted to the selected word line. The gate decoder selects an addressed word line in the selected block. The sub-decoder drives the addressed word line into the selected state in accordance with output signals (voltages) of these block decoder and gate decoder.
The sub-decoder is constructed by a complementary MOS (CMOS) inverter Power supply voltages (source voltages) levels on high and low sides of each sub-decoder are set in accordance with the output signal of the block decoder, and the output signal of the gate decoder is supplied to gates of the transistors of the sub-decoder.
The sub-decoder includes a P-channel MOS transistor (insulation gate field effect transistor), and an N-channel MOS transistor. Thus, in the sub-decoder, a well region is divided into an N-well region in which the P-channel MOS transistor is arranged and a P-well region in which the N-channel MOS transistor is arranged.
The P-channel MOS transistor and the N-channel MOS transistor constructing one sub-decoder element are arranged in alignment along a word line extending direction. By connecting the drains of the P-channel and N-channel MOS transistors of constructing one sub-decoder element to a word line extending linearly, a interconnection layout is simplified, and the arrangement of the transistors constructing the sub-decoder elements is simplified, which reduces a layout area of the sub-decoders.
However, in the case where the sub-decoder element constructed by the CMOS inverter is used, the following problem arises with the miniaturization of the memory cells. As the memory cells are more and more miniaturized, a length in size of one block in the column direction (source diffusion layer and drain diffusion layer) becomes smaller. In the sub-decoder constructed by the CMOS inverter, a source potential of the transistor is common to a well potential, and a common source voltage is supplied to the NMOS transistors and another common source voltage is to the PMOS transistors. Accordingly, between the adjacent sub-decoder elements, a source region can be shared by the N-channel MOS transistors and the source region can be shared by the P-channel MOS transistors. Thus, the transistors of the same conductivity type of two sub-decoder elements can be arranged in a common active region. However, since drain regions are connected to different word lines between the adjacent sub-decoder elements, the active region needs to be divided for each two sub-decoder elements. Therefore, an isolation region needs to be provided between the adjacent active regions, which causes a problem that shrinking of the layout of the sub-decoder cannot follow the miniaturization of the memory cells.
In a flash memory, an example of a memory cell configuration utilizing an assist gate is disclosed in Reference 2 (Japanese Patent Laying-Open No. 2001-028428). In Reference 2, a memory array is divided into blocks, writing/erasure/reading of data of memory cells are performed on a block basis. A sub-decoder for driving a word line has a CMOS configuration, and drives a word line in accordance with a gate signal and a block selection signal. Accordingly, in Reference 2 also, the problem with the layout of the sub-decoders also arises.
As an approach for solving this problem, in Reference 3 (Japanese Patent Laying-Open No. 2003-141887), there is suggested a method in which the elements of a sub-decoder are all constructed by N-channel MOS transistors. In the case where these sub-decoder elements are formed of N-channel MOS transistors, the diffusion layer (active region) is not needed to be divided for each two MOS transistors, and a common active region can be provided for a larger number of MOS transistors. In addition, the element transistors are all N-channel MOS transistors, and the region for implementing well isolation is not necessary, which can reduce a layout area of the sub-decoder.
However, in the flash memory, the memory cell is formed of a stacked gate type transistor having a floating gate. When data is written in a memory cell (electrons are injected to the floating gate), it is required to apply a high voltage of 17 V, for example, to a word line through the N-channel MOS transistor. In this case, in consideration of threshold voltage loss at the N-channel MOS transistor, a voltage higher than the word line voltage, for example, about 20 V is necessary to a gate of the N-channel MOS transistor. Thus, a voltage higher than breakdown voltage of the MOS transistor is applied, which can cause element destruction. In addition, in the case where such a high voltage is generated utilizing a charger pump circuit, for example, the number of stages of the charger pump needs to be increased, and accordingly, an area of an internal power supply circuit for generating the high voltage is increased.
By utilizing a high breakdown voltage transistor having a thick gate insulating film for the MOS transistor, the problem of the element destruction can be solved. However, when a high voltage is applied, a parasite MOS in an isolation region is produced, and leakage current is generated through such parasitic MOS, which increases power consumption. Further, there arises a problem that dielectric breakdown of the isolation region can occur.
A configuration for preventing such leakage current through the parasitic MOS of the sub-decoder is disclosed in Reference 3 (Japanese Patent Laying-Open No. 2005-243211). In this configuration shown in Reference 3, in an NAND type flash memory, in the erasure operation mode in which a high voltage is applied to memory cell well region, a negative voltage for preventing leakage current is applied to the well region of an X decoder. In the erasure operation, a power supply voltage Vcc of 4.5 V, for example, is applied to a gate of a high voltage transistor of the X decoder of a selected block. Also, a voltage lower than the power supply voltage by a threshold voltage of the high voltage transistor is applied to a gate of a transistor that selects a memory cell string to maintain the transistor in an off state, so that a ground line (source line) and a string line (drain) of the selected memory cell block are set into an electrically floating state. A well potential of the memory cell array is set to a high voltage of about 20 V in the erasure. In a non-selected memory block, the ground voltage is applied to the gate of the high voltage transistor, and similarly, the well potential is also set to a negative voltage to maintain the word line, the string line, and the ground line in the electrically floating state. This reduces leakage current by the high voltage transistor of the X decoder in the non-selected memory cell block. That is, in the non-selected memory block, by maintaining the word line in the electrically floating state, the non-selected memory cell is prevented from being subjected to erasure disturbance by the array well voltage due to a decrease in the word line voltage resulting from the leakage current in the high voltage transistor of the X decoder.
Further, a configuration in which leakage current between transfer gate transistors that transmit a word line driving voltage in X decoders is suppressed is disclosed in Reference 4 (Japanese Patent Laying-Open No. 2004-185660). In this configuration disclosed in Reference 4, the arrangement of the transfer gate transistors that transmit a high voltage is devised to avoid the occurrence of a state where the transfer gate transistors, to which a ground voltage, a program voltage and a pass voltage are applied respectively, are arranged adjacently. Thus, a parasitic MOS transistor, to which an on-voltage higher than the ground voltage, the pass voltage and the program voltage is applied, is prevented from being formed between the adjacent transfer gates, thereby suppressing the generation of channel leakage in this element isolation insulating film.
In Reference 1, by equalizing the lower source voltage of two transistor source potentials of the N-channel type transistors to the well potential, the N-channel MOS transistors of the sub-decoder elements are formed in a common active region to suppress the provision of the element isolation region, which reduces a chip area and achieves a high-speed operation.
However, in the configuration shown in Reference 1, since high voltage is used in the writing, leakage current through a parasitic MOS is also generated in the sub-decoder, so that current consumption is increased, and memory characteristics are deteriorated. Accordingly, in the case where distances between an isolation region end and an isolation region end, and between the isolation region and a gate electrode end are increased in order to suppress the leakage current through the parasitic MOS, the layout area of the sub-decoder is increased, which makes the miniaturization difficult. In Reference 1, the layout of the sub-decoder following the cell miniaturization is not considered.
In the configuration shown in Reference 2, the cell isolating insulation film region is eliminated through the use of an assist gate. However, in Reference 2, the CMOS inverter is utilized for the sub-decoder element, and the reduction in layout area of the sub-decoder is not considered. In addition, although a hierarchical structure is used for the decoder configuration, a common source signal is supplied to the sub-decoder elements in a memory block, and a word line is selected by a gate signal. In the decoder configuration in which the source signal is applied to individual sub-decoder elements, no consideration is given to the problem of the parasitic MOS due to high voltage.
In the configuration shown in Reference 3, the well potential of the X decoder is changed in the erasure, to maintain the word lines of the non-selected block in the electrically floating state, thereby avoiding the problem that leakage current is generated in the high voltage transistor of the X decoder. However, in the configuration shown in Reference 3, the well potential is adjusted in common to the X decoders in all blocks. Accordingly, load on a well potential generating unit becomes large, which makes it difficult to change the well potential at high speed. In addition, in Reference 3, leakage current for the non-selected word line is considered, but leakage current through the parasitic MOS by high voltage in the isolation region between the sub-decoder elements, and breakdown voltage of the isolation region are not considered.
In the configuration disclosed in Reference 3, the configuration of the transfer gate type decoder using a high voltage transistor is merely considered, and no consideration is given to a decoder configuration having a word line driver such as a CMOS inverter.
Reference 4 considers an issue of the X decoder of the NAND type flash memory, and particularly, intends to avoid the occurrence of leakage current through the parasitic MOS between the adjacent transfer gates. The arrangement of the transfer gates of the decoder is adjusted such that even if a parasitic MOS is formed, such voltages are applied to the parasitic MOS as to reduce the leakage current by a back-gate bias effect at the parasitic MOS. In addition, a voltage of a selected gate that transmits a pass voltage is made lower than a programming high voltage, so that even when the pass voltage and the ground voltage are applied to the drain and the source of the parasitic MOS, respectively, element dielectric breakdown characteristics is maintained.
However, in Reference 4, similarly to Reference 3, no consideration is given to the decoder configuration having a word line driver unit such as a CMOS inverter. In addition, no consideration is given to the problem of deterioration in isolation characteristics depending on a distance between a gate electrode of the transfer gate and a distance of an isolation region. Further, no consideration is given to dielectric breakdown characteristics between an active region end and the gate electrode in the transfer gate itself. Furthermore, the miniaturization of the sub-decoder element is not considered.